1. Field of the Invention
The present invention relates to stacked gate field effect transistor (FET) devices. More particularly, the present invention relates to stacked gate field effect transistor (FET) devices with enhanced performance.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices and over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of semiconductor integrated circuit microelectronic fabrication are conventional field effect transistor (FET) devices which are employed as switching elements within both logic semiconductor integrated circuit microelectronic fabrications and memory semiconductor integrated circuit microelectronic fabrications. Also known in the art of semiconductor integrated circuit microelectronic fabrication are stacked gate field effect transistor (FET) devices which in contrast to conventional field effect transistor (FET) devices employ gate electrode stacks comprising floating gate electrodes having formed thereupon inter-gate electrode dielectric layers in turn having formed thereupon control gate electrodes. As is understood by a person skilled in the art, stacked gate field effect transistor (FET) devices differ from conventional field effect transistor (FET) devices insofar as stacked gate field effect transistor (FET) devices provide for non-volatile digital data storage within the floating gate electrodes within stacked gate field effect transistor (FET) devices.
While stacked gate field effect transistor (FET) devices are thus clearly desirable in the art of semiconductor integrated circuit microelectronic fabrication, stacked gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, stacked gate field effect transistor (FET) devices are often difficult to fabricate within semiconductor integrated circuit microelectronic fabrications with enhanced performance.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to fabricate stacked gate field effect transistor (FET) devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various stacked gate field effect transistor (FET) devices, and methods for fabrication thereof, have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication.
Included among the stacked gate field effect transistor (FET) devices and methods for fabrication thereof, but not limited among the stacked gate field effect transistor (FET) devices and methods for fabrication thereof, are stacked gate field effect transistor (FET) devices and methods for fabrication thereof disclosed within: (1) Baker et al., in U.S. Pat. No. 4,852,062 (a stacked gate field effect transistor (FET) device and method for fabrication thereof having enhanced performance incident to fabricating the stacked gate field effect transistor (FET) device with asymmetrically spaced source/drain regions); and (2) Chen et al., in U.S. Pat. No. 6,291,905 (a stacked gate field effect transistor (FET) device and method for fabrication thereof with enhanced manufacturability incident to fabricating the stacked gate field effect transistor (FET) device employing a damascene method)
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods and materials which may be employed for fabricating stacked gate field effect transistor (FET) devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a stacked gate field effect transistor (FET) device and a method for fabricating the stacked gate field effect transistor (FET) device.
A second object of the present invention is to provide a stacked gate field effect transistor (FET) device and a method for fabrication thereof in accord with the first object of the present invention, wherein the stacked gate field effect transistor (FET) device is fabricated with enhanced performance.
A third object of the present invention is to provide a stacked gate field effect transistor (FET) device and a method for fabrication thereof in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a stacked gate field effect transistor (FET) device and a method for fabricating the stacked gate field effect transistor (FET) device. Similarly, the present invention also provides a related method for operating the stacked gate field effect transistor (FET) device.
To practice the method of the present invention, there is first provided a semiconductor substrate having an active region defined therein. There is then formed upon the active region of the semiconductor substrate a tunneling dielectric layer. There is then formed upon the tunneling dielectric layer a floating gate electrode. There is then formed upon the floating gate electrode an inter-gate electrode dielectric layer. There is then formed upon the inter-gate electrode dielectric layer a control gate electrode which is typically and preferably aligned at least in part with the floating gate electrode. Finally, there is also formed adjacent a pair of opposite edges of the floating gate electrode a pair of source/drain regions. Within the present invention, at least one of: (1) the floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) the pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.
The present invention provides a stacked gate field effect transistor (FET) device and a method for fabricating the stacked gate field effect transistor (FET) device, wherein the stacked gate field effect transistor (FET) device is fabricated with enhanced performance.
The present invention realizes the foregoing object by fabricating a stacked gate field effect transistor (FET) device wherein at least one of: (1) a floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) a pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering to provide a stacked gate field effect transistor (FET) device in accord with the present invention. Since it is thus at least in part a specific process ordering which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.